A Research Platform for Singapore

Sensing and Management for Agile Transport

Overview

SMAT focusses on developing intelligent sensing technologies to support and enforce traffic management of the SRT layer. This involves the development of robust and secure vision based sensing methods for collaborative computing and crowd sourcing. The underlying research in SMAT will lead to a better understanding of the advantage and limitations of utilizing real-time data to assist travellers in an Agile Transportation System.

Research

Architecture-Aware Algorithms for Low-Cost Sensing

In order to provide for scalable vision based crowd sourcing for a dense urban public transport system, such as in Singapore, low-complexity sensing techniques are critical to justify mass volume adoption. Architecture-efficient algorithms are being developed to implement low-complexity and real-time vision-based traffic sensors. The robustness of such algorithms will be evaluated to ensure they withstand the varying weather conditions and complex conditions on a road segment.

Techniques for Vehicle Breakdown and Accident Detection

Vision based techniques are being devised to accurately establish traffic incidents and traffic violations. Computationally inexpensive computer vision algorithms are being developed to perform localized monitoring of current traffic condition. Vision based sensors will be used to detect traffic law violations (e.g. entering priority lanes, illegal parking in priority lanes, illegal turns, etc.). It is envisaged that mass-deployable real-time law enforcement solutions would ultimately ensure smooth traffic flow for SRTs.

Real-Time Scene Understanding for Congestion Management

Persistent congestions can be automatically identified through real-time scene understanding techniques. Crowd sourcing methods are being adopted by installing scene understanding sensors in vehicles to detect congestion. The relevant authorities can then take necessary actions to alleviate such unanticipated persistent congestion patterns that emerge over time.

Passive Sensing Techniques using Smartphone Location Data

The problem of inferring the mobility details of users from sequences of smartphone location samples involves considerable uncertainty, especially if the data is noisy and temporally sparse. Therefore, we intend to adopt a suitable probabilistic framework for solving this problem. To be able to process real-time data from a large number of users, the algorithms should have low latency and high computational efficiency. Therefore, are exploring optimization techniques to reduce the runtime and latency of the proposed methods. The developed solutions will be subjected to extensive evaluations using both real data as well as synthetic data obtained from traffic simulation environments. Robust statistical methods will be explored for aggregating information extracted from individual mobility traces in order to estimate the overall travel demand.

Secure Autonomous Traffic Security

A security-enabled sensory network protocol that satisfies real-time constraints is being developed using a virtual traffic simulation environment. The proposed network protocol will be deployed and benchmarked with off-the-shelf micro-controllers and FPGA development boards. Side-channel attack/tamper-resistant low-cost cryptographic accelerators for Internet of Things (IoT) communication will be developed such that the encryption/decryption modules are physically resistant to reasonably sophisticated side-channel attacks.

 

Publications

[1]K. Garg, S. K. Lam, T. Srikanthan, and A. Vedika, “Real-time road traffic density estimation using block variance,” in Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision (WACV), Lake Placid, NY, USA, Mar. 2016, pp. 1–9, DOI: 10.1109/WACV.2016.7477607.
 
@inproceedings{garg2016realSMAT,
title={Real-Time Road Traffic Density Estimation Using Block Variance},
author={Garg, Kratika and Lam, Siew Kei and Srikanthan, Thambipillai and Vedika, Agarwal},
booktitle={Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision (WACV)},
year={2016},
month=mar,
pages={1--9},
location={Lake Placid, NY, USA},
doi={10.1109/WACV.2016.7477607},
}
[2]D. Wijesundera, A. Prakash, S. K. Lam, and T. Srikanthan, “Exploiting configuration dependencies for rapid area-efficient customization of soft-core processors,” in Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, Sankt Goar, Germany, May 2016, pp. 163–172, ISBN: 978-1-4503-4320-6, DOI: 10.1145/2906363.2906385.
 
@inproceedings{wijesundera2016exploitingSMAT,
title={Exploiting Configuration Dependencies for Rapid Area-Efficient Customization of Soft-Core Processors},
author={Wijesundera, Deshya and Prakash, Alok and Lam, Siew Kei and Srikanthan, Thambipillai},
booktitle={Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems},
year={2016},
month=may,
pages={163--172},
location={Sankt Goar, Germany},
isbn={978-1-4503-4320-6},
doi={10.1145/2906363.2906385},
}
[3]A. Chattopadhyay, V. Pudi, A. Baksi, and T. Srikanthan, “FPGA based cyber security protocol for automated traffic monitoring systems: proposal and implementation,” in Proceedings of the 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, USA, Jul. 2016, pp. 18–23, DOI: 10.1109/ISVLSI.2016.97.
 
@inproceedings{chattopadhyay2016fpgaSMAT,
title={{FPGA} Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation},
author={Chattopadhyay, Anupam and Pudi, Vikramkumar and Baksi, Anubhab and Srikanthan, Thambipillai},
booktitle={Proceedings of the 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year={2016},
month=jul,
pages={18--23},
location={Pittsburgh, PA, USA},
doi={10.1109/ISVLSI.2016.97},
}
[4]M. Wu, C. Zhou, and T. Srikanthan, “Robust and low complexity obstacle detection and tracking,” in 2016 IEEE 19th International Conference on Intelligent Transportation Systems (ITSC), Brazil, Nov. 2016, pp. 1249–1254, DOI: 10.1109/ITSC.2016.7795717.
 
@inproceedings{Wu2016RobustSMAT,
title={Robust and Low Complexity Obstacle Detection and Tracking},
author={Wu, Meiqing and Zhou, Chengju and Srikanthan, Thambipillai},
booktitle={2016 IEEE 19th International Conference on Intelligent Transportation Systems (ITSC)},
year={2016},
month=nov,
pages={1249--1254},
location={Brazil},
doi={10.1109/ITSC.2016.7795717},
}
[5]G. R. Jagadeesh and T. Srikanthan, “Heuristic optimizations for high-speed low-latency online map matching with probabilistic sequence models,” in Proceedings of the 19th International Conference on Intelligent Transportation Systems (ITSC 2016), Rio de Janeiro, Brazil, Nov. 2016, pp. 2565–2570, DOI: 10.1109/ITSC.2016.7795968.
 
@inproceedings{jagadeesh2016heuristicSMAT,
title={Heuristic Optimizations for High-speed Low-Latency Online Map Matching with Probabilistic Sequence Models},
author={Jagadeesh, George Rosario and Srikanthan, Thambipillai},
booktitle={Proceedings of the 19th International Conference on Intelligent Transportation Systems (ITSC 2016)},
year={2016},
month=nov,
pages={2565--2570},
location={Rio de Janeiro, Brazil},
doi={10.1109/ITSC.2016.7795968},
}
[6]D. Wijesundera, A. Prakash, and T. Srikanthan, “Rapid design space exploration for soft core processor customization and selection,” in Proceedings of the 2016 International Conference on Field-Programmable Technology (FPT), Xi'an, China, Dec. 2016, pp. 185–188, DOI: 10.1109/FPT.2016.7929529.
 
@inproceedings{wijesundera2016rapidSMAT,
title={Rapid Design Space Exploration for Soft Core Processor Customization and Selection},
author={Wijesundera, Deshya and Prakash, Alok and Srikanthan, Thambipillai},
booktitle={Proceedings of the 2016 International Conference on Field-Programmable Technology (FPT)},
year={2016},
month=dec,
pages={185--188},
location={Xi'an, China},
doi={10.1109/FPT.2016.7929529},
}
[7]V. Pudi, A. Chattopadhyay, and T. Srikanthan, “Modified projected landweber method for compressive-sensing reconstruction of images with non-orthogonal matrices,” in Proceedings of the 2016 International Symposium on Integrated Circuits (ISIC), Singapore, Dec. 2016, pp. 1–4, DOI: 10.1109/ISICIR.2016.7829716.
 
@inproceedings{pudi2016modifiedSMAT,
title={Modified Projected Landweber Method for Compressive-Sensing Reconstruction of Images with Non-Orthogonal Matrices},
author={Pudi, Vikramkumar and Chattopadhyay, Anupam and Srikanthan, Thambipillai},
booktitle={Proceedings of the 2016 International Symposium on Integrated Circuits (ISIC)},
year={2016},
month=dec,
pages={1--4},
location={Singapore},
doi={10.1109/ISICIR.2016.7829716},
}
[8]A. Easwaran, A. Chattopadhyay, and S. Bhasin, “A systematic security analysis of real-time cyber-physical systems,” in Proceedings of the 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, Jan. 2017, pp. 206–213, DOI: 10.1109/ASPDAC.2017.7858321.
 
@inproceedings{easwaran2017systematicSMAT,
title={A Systematic Security Analysis of Real-Time Cyber-physical Systems},
author={Easwaran, Arvind and Chattopadhyay, Anupam and Bhasin, Shivam},
booktitle={Proceedings of the 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)},
year={2017},
month=jan,
pages={206--213},
location={Chiba, Japan},
doi={10.1109/ASPDAC.2017.7858321},
}
[9]D. Mukhopadhyay, V. Pudi, and A. Chattopadhyay, “SHA-3 implementation using reram based in-memory computing architecture,” in Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, Mar. 2017, pp. 325–330, DOI: 10.1109/ISQED.2017.7918336.
 
@inproceedings{bhattacharjee2017shaSMAT,
title={{SHA-3} Implementation Using ReRAM based In-Memory Computing Architecture},
author={Mukhopadhyay, Debdeep and Pudi, Vikramkumar and Chattopadhyay, Anupam},
booktitle={Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED)},
year={2017},
month=mar,
pages={325--330},
location={Santa Clara, CA, USA},
doi={10.1109/ISQED.2017.7918336},
}
[10]A. Chattopadhyay, A. Prakash, and M. Shafique, “Secure cyber-physical systems: current trends, tools and open research problems,” in Proceedings of the 2017 Design, Automation Test in Europe Conference (DATE), Lausanne, Switzerland, Mar. 2017, pp. 1104–1109, DOI: 10.23919/DATE.2017.7927154.
 
@inproceedings{chattopadhyay2017secureSMAT,
title={Secure Cyber-Physical Systems: Current Trends, Tools and Open Research Problems},
author={Chattopadhyay, Anupam and Prakash, Alok and Shafique,Muhammad},
booktitle={Proceedings of the 2017 Design, Automation Test in Europe Conference (DATE)},
year={2017},
month=mar,
pages={1104--1109},
location={Lausanne, Switzerland},
doi={10.23919/DATE.2017.7927154},
}
[11]K. Herath, A. Prakash, J. Guiyuan, and T. Srikanthan, “Communication-aware partitioning for energy optimization of large FPGA designs,” in Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, Alberta, Canada, May 2017, pp. 407–410, DOI: 10.1145/3060403.3060441.
 
@inproceedings{Herath2017CPECommunicationSMAT,
title={Communication-aware Partitioning for Energy Optimization of Large {FPGA} Designs},
author={Herath, Kalindu and Prakash, Alok and Guiyuan, Jiang and Srikanthan, Thambipillai},
booktitle={Proceedings of the on Great Lakes Symposium on VLSI 2017},
year={2017},
month=may,
pages={407--410},
location={Banff, Alberta, Canada},
doi={10.1145/3060403.3060441},
}
[12]D. Wijesundera, A. Ihalage, A. Prakash, and T. Srikanthan, “High speed performance estimation of embedded hard-core processors in FPGA-based socs,” in Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Bochum, Germany, Jun. 2017, pp. 2:1–2:6, ISBN: 978-1-4503-5316-8, DOI: 10.1145/3120895.3120902.
 
@inproceedings{wijesundera2017highSMAT,
title={High Speed Performance Estimation of Embedded Hard-core Processors in {FPGA}-based SoCs},
author={Wijesundera, Deshya and Ihalage, Achintha and Prakash, Alok and Srikanthan, Thambipillai},
booktitle={Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies},
year={2017},
month=jun,
pages={2:1--2:6},
location={Bochum, Germany},
isbn={978-1-4503-5316-8},
doi={10.1145/3120895.3120902},
}
[13]G. Jiang, S. K. Lam, S. Yidan, L. Tu, and J. Wu, “Joint charging tour planning and depot positioning for wireless sensor networks using mobile chargers,” IEEE/ACM Transactions on Networking, vol. 25, pp. 2250–2266, Aug. 2017, ISSN: 1063-6692, DOI: 10.1109/TNET.2017.2684159.
 
@article{jiang2017jointSMAT,
title={Joint Charging Tour Planning and Depot Positioning for Wireless Sensor Networks Using Mobile Chargers},
author={Jiang, Guiyuan and Lam, Siew Kei and Yidan, Sun and Tu, Lijia and Wu, Jigang},
journal={IEEE/ACM Transactions on Networking},
volume={25},
year={2017},
month=aug,
pages={2250--2266},
issn={1063-6692},
doi={10.1109/TNET.2017.2684159},
}
[14]S. P. Kadiyala, V. K. Pudi, and S. K. Lam, “Approximate compressed sensing for hardware-efficient image compression,” in Proceedings of the 30th IEEE International System-on-Chip Conference (SOCC), Munich, Germany, Sep. 2017, pp. 340–345, DOI: 10.1109/SOCC.2017.8226074.
 
@inproceedings{kadiyala2017approximateSMAT,
title={Approximate Compressed Sensing for Hardware-Efficient Image Compression},
author={Kadiyala, Sai Praveen and Pudi, Vikram Kumar and Lam, Siew Kei},
booktitle={Proceedings of the 30th IEEE International System-on-Chip Conference (SOCC)},
year={2017},
month=sep,
pages={340--345},
location={Munich, Germany},
doi={10.1109/SOCC.2017.8226074},
}
[15]C. Zhou, M. Wu, and S. K. Lam, “Group cost-sensitive boosting with multi-scale decorrelated filters for pedestrian detection,” in Proceedings of the Twenty Eighth British Machine Vision Conference, London, UK, Sep. 2017, in press.
 
@inproceedings{zhougroupSMAT,
title={Group Cost-Sensitive Boosting with Multi-scale Decorrelated Filters for Pedestrian Detection},
author={Zhou, Chengju and Wu, Meiqing and Lam, Siew Kei},
booktitle={Proceedings of the Twenty Eighth British Machine Vision Conference},
year={2017},
month=sep,
location={London, UK},
}
[16]S. D. Kumar, S. Patranabis, J. Breier, D. Mukhopadhyay, S. Bhasin, A. Chattopadhyay, and A. Baksi, “A practical fault attack on ARX-like ciphers with a case study on ChaCha20,” in Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Taipei, Taiwan, Sep. 2017, pp. 33–40, DOI: 10.1109/FDTC.2017.14.
 
@inproceedings{kumar2017practicalSMAT,
title={A Practical Fault Attack on {ARX}-Like Ciphers with a Case Study on {ChaCha20}},
author={Kumar, SV Dilip and Patranabis, Sikhar and Breier, Jakub and Mukhopadhyay, Debdeep and Bhasin, Shivam and Chattopadhyay, Anupam and Baksi, Anubhab},
booktitle={Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)},
year={2017},
month=sep,
pages={33--40},
location={Taipei, Taiwan},
doi={10.1109/FDTC.2017.14},
}
[17]K. Garg, A. Prakash, and T. Srikanthan, “Low complexity techniques for robust real-time traffic incident detection,” in Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems (ITSC), Yokohama, Japan, Oct. 2017, pp. 1–8, DOI: 10.1109/ITSC.2017.8317740.
 
@inproceedings{garg2017lowSMAT,
title={Low Complexity Techniques for Robust Real-Time Traffic Incident Detection},
author={Garg, Kratika and Prakash, Alok and Srikanthan, Thambipillai},
booktitle={Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems (ITSC)},
year={2017},
month=oct,
pages={1--8},
location={Yokohama, Japan},
doi={10.1109/ITSC.2017.8317740},
}
[18]C. Zhou, M. Wu, and S. K. Lam, “Fast and accurate pedestrian detection using dual-stage group cost-sensitive realboost with vector form filters,” in Proceedings of the 25th ACM Multimedia, Mount View, USA, Oct. 2017, pp. 735–743, DOI: 10.1145/3123266.3123303.
 
@inproceedings{zhou2017fastSMAT,
title={Fast and Accurate Pedestrian Detection using Dual-Stage Group Cost-Sensitive RealBoost with Vector Form Filters},
author={Zhou, Chengju and Wu, Meiqing and Lam, Siew Kei},
booktitle={Proceedings of the 25th ACM Multimedia},
year={2017},
month=oct,
pages={735--743},
location={Mount View, USA},
doi={10.1145/3123266.3123303}
}
[19]P. Thilina, A. Prakash, and T. Srikanthan, “A scalable heuristic algorithm for demand responsive transportation for first mile transit,” in Proceedings of the 21st IEEE International Conference on Intelligent Engineering Systems, Larnaca, Cyprus, Oct. 2017, pp. 157–162, DOI: 10.1109/INES.2017.8118547.
 
@inproceedings{perera2017scalableSMAT,
title={A Scalable Heuristic Algorithm for Demand Responsive Transportation for First Mile Transit},
author={Thilina, Perera and Prakash, Alok and Srikanthan, Thambipillai},
booktitle={Proceedings of the 21st IEEE International Conference on Intelligent Engineering Systems},
year={2017},
month=oct,
pages={157--162},
location={Larnaca, Cyprus},
doi={10.1109/INES.2017.8118547}
}
[20]S. Lam, T. C. Lim, M. Wu, B. Cao, and B. Jasani, “Data-path unrolling with logic folding for area-time-efficient FPGA-based FAST corner detector,” Journal of Real-Time Image Processing, Oct. 2017, DOI: 10.1007/s11554-017-0725-0.
 
@article{Lam2017DataSMAT,
title={Data-Path Unrolling with Logic Folding for Area-time-efficient {FPGA}-based {FAST} Corner Detector},
author={Lam, Siew-Kei and Lim, Teck Chuan and Wu, Meiqing and Cao, Bin and Jasani, Bhavan},
journal={Journal of Real-Time Image Processing},
year={2017},
month=oct,
doi={10.1007/s11554-017-0725-0},
}
[21]A. Chattopadhyay and K. Y. Lam, “Security of autonomous vehicle as a cyber-physical system,” in Proceedings of the 7th IEEE International Symposium on Embedded Computing and System Design (ISED-2017), India, Dec. 2017, pp. 1–6, DOI: 10.1109/ISED.2017.8303906.
 
@inproceedings{chattopadhyay2017securitySMAT,
title={Security of Autonomous Vehicle as a Cyber-Physical System},
author={Chattopadhyay, Anupam and Lam, Kwok Yan},
booktitle={Proceedings of the 7th IEEE International Symposium on Embedded Computing and System Design (ISED-2017)},
year={2017},
month=dec,
pages={1--6},
location={India},
doi={10.1109/ISED.2017.8303906}
}
[22]G. R. Jagadeesh and T. Srikanthan, “Online map-matching of noisy and sparse location data with hidden markov and route choice models,” IEEE Transactions on Intelligent Transportation Systems, vol. 18, no. 9, pp. 2423–2434, Dec. 2017, DOI: 10.1109/TITS.2017.2647967.
 
@article{jagadeesh2017onlineSMAT,
title={Online Map-Matching of Noisy and Sparse Location Data with Hidden Markov and Route Choice Models},
author={Jagadeesh, George Rosario and Srikanthan, Thambipillai},
journal={IEEE Transactions on Intelligent Transportation Systems},
volume={18},
number={9},
year={2017},
month=dec,
pages={2423--2434},
doi={10.1109/TITS.2017.2647967}
}
[23]S. K. Lam, R. K. Bijarniya, and M. Wu, “Lowering dynamic power in stream-based harris corner detection architecture,” in Proceedings of the 2017 International Conference on Field Programmable Technology (ICFPT), Melbourne, VIC, Australia, Dec. 2017, pp. 176–182, DOI: 10.1109/FPT.2017.8280136.
 
@inproceedings{lam2017loweringSMAT,
title={Lowering Dynamic Power in Stream-Based Harris Corner Detection Architecture},
author={Lam, Siew Kei and Bijarniya, Rakesh Kumar and Wu, Meiqing},
booktitle={Proceedings of the 2017 International Conference on Field Programmable Technology (ICFPT)},
year={2017},
month=dec,
pages={176--182},
location={Melbourne, VIC, Australia},
doi={10.1109/FPT.2017.8280136},
}
[24]M. Wu, S. K. Lam, and T. Srikanthan, “A framework for fast and robust visual odometry,” IEEE Transactions on Intelligent Transportation Systems, vol. 18, no. 12, pp. 3433–3448, Dec. 2017, DOI: 10.1109/TITS.2017.2685433.
 
@article{wu2017frameworkSMAT,
title={A Framework for Fast and Robust Visual Odometry},
author={Wu, Meiqing and Lam, Siew Kei and Srikanthan, Thambipillai},
journal={IEEE Transactions on Intelligent Transportation Systems},
volume={18},
number={12},
year={2017},
month=dec,
pages={3433--3448},
doi={10.1109/TITS.2017.2685433}
}
[25]A. Burg, A. Chattopadhyay, and K. Y. Lam, “Wireless communication and security issues for cyber-physical systems and the internet-of-things,” Proceedings of the IEEE, vol. 106, pp. 38–60, Jan. 2018, DOI: 10.1109/JPROC.2017.2780172.
 
@article{Andreas2018wirelessSMAT,
title={Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things},
author={Burg, Andreas and Chattopadhyay, Anupam and Lam, Kwok-Yan},
journal={Proceedings of the IEEE},
year={2018},
month=jan,
volume={106},
pages={38--60},
doi={10.1109/JPROC.2017.2780172},
}
[26]M. Alam, S. Bhattacharya, D. Mukhopadhyay, and A. Chattopadhyay, “RAPPER: ransomware prevention via performance counters,” Cryptography and Security, vol. 25, pp. 1–7, Feb. 2018, in press.
 
@article{alam2018rapperSMAT,
title={{RAPPER}: Ransomware Prevention via Performance Counters},
author={Alam, Manaar and Bhattacharya, Sarani and Mukhopadhyay, Debdeep and Chattopadhyay, Anupam},
journal={Cryptography and Security},
volume={25},
year={2018},
month=feb,
pages={1--7},
}
[27]M. Khairallah, R. Sadhukhan, R. Samanta, J. Breier, S. Bhasin, R. S. Chakraborty, A. Chattopadhyay, and D. Mukhopadhyay, “DFARPA: differential fault attack resistant physical design automation,” in Proceedings of the 2018 Design, Automation Test in Europe Conference and Exhibition (DATE), Dresden, Germany, Mar. 2018, pp. 1171–1174, DOI: 10.23919/DATE.2018.8342190.
 
@inproceedings{khairallah2018dfarpaSMAT,
title={{DFARPA}: Differential Fault Attack Resistant Physical Design Automation},
author={Khairallah, Mustafa and Sadhukhan, Rajat and Samanta, Radhamanjari and Breier, Jakub and Bhasin, Shivam and Chakraborty, Rajat Subhra and Chattopadhyay, Anupam and Mukhopadhyay, Debdeep},
booktitle={Proceedings of the 2018 Design, Automation Test in Europe Conference and Exhibition (DATE)},
year={2018},
month=mar,
pages={1171--1174},
location={Dresden, Germany},
doi={10.23919/DATE.2018.8342190},
}
[28]D. Bhattacharjee, L. Amaru, and A. Chattopadhyay, “Technology-aware logic synthesis for ReRAM based in-memory computing,” in 2018 Design, Automation Test in Europe Conference Exhibition (DATE), Dresden, Germany, Mar. 2018, pp. 1435–1440, DOI: 10.23919/DATE.2018.8342237.
 
@inproceedings{Bhattacharjee2018TechnologySMAT,
title={Technology-aware Logic Synthesis for {ReRAM} Based In-memory Computing},
author={Bhattacharjee, Debjyoti and Amaru, Luca and Chattopadhyay, Anupam},
booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
year={2018},
month=mar,
pages={1435--1440},
location={Dresden, Germany},
doi={10.23919/DATE.2018.8342237},
}
[29]V. Pudi, A. Chattopadhyay, and K. Y. Lam, “Secure and lightweight compressive sensing using stream cipher,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, pp. 371–375, Mar. 2018, ISSN: 1549-7747, DOI: 10.1109/TCSII.2017.2715659.
 
@article{pudi2018secureSMAT,
title={Secure and Lightweight Compressive Sensing Using Stream Cipher},
author={Pudi, Vikramkumar and Chattopadhyay, Anupam and Lam,Kwok Yan},
journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
volume={65},
year={2018},
month=mar,
pages={371--375},
issn={1549-7747},
doi={10.1109/TCSII.2017.2715659},
}
[30]T. Vatwani, A. Dutt, D. Bhattacharjee, and A. Chattopadhyay, “Floating point multiplication mapping on ReRAM based in-memory computing architecture,” in 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), Pune, India, Apr. 2018, pp. 439–444, DOI: 10.1109/VLSID.2018.104.
 
@inproceedings{vatwani2018FloatingSMAT,
title={Floating Point Multiplication Mapping on {ReRAM} Based In-memory Computing Architecture},
author={Vatwani, Tarun and Dutt, Arko and Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
booktitle={2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)},
year={2018},
month=apr,
pages={439--444},
location={Pune, India},
doi={10.1109/VLSID.2018.104},
}
[31]S. Kumar, J. H. Yahya, and A. Chattopadhyay, “Efficient hardware accelerator for NORX authenticated encryption,” in Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018), Florence, May 2018, pp. 195–198, DOI: 10.1109/ISCAS.2018.8351145.
 
@inproceedings{kumar2018efficientSMAT,
title={Efficient Hardware Accelerator for {NORX} Authenticated Encryption},
author={Kumar, Sachin and Yahya, Jawad Haj and Chattopadhyay, Anupam},
booktitle={Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018)},
year={2018},
month=may,
pages={195--198},
location={Florence},
doi={10.1109/ISCAS.2018.8351145},
}
[32]V. Pudi, A. Chattopadhyay, and L. Kwok-Yan, “Efficient and lightweight quantized compressive sensing using mu-law,” in Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018), Florence, May 2018, pp. 1–5, DOI: 10.1109/ISCAS.2018.8351505.
 
@inproceedings{pudi2018efficientSMAT,
title={Efficient and Lightweight Quantized Compressive Sensing Using Mu-Law},
author={Pudi, Vikramkumar and Chattopadhyay, Anupam and Kwok-Yan, Lam},
booktitle={Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018)},
year={2018},
month=may,
pages={1--5},
location={Florence},
doi={10.1109/ISCAS.2018.8351505},
}
[33]M. M. Wong, H. Y. Jawad, S. Suman, and A. Chattopadhyay, “A new high throughput and area efficient SHA-3 implementation,” in Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018), Florence, May 2018, pp. 1–5, DOI: 10.1109/ISCAS.2018.8351649.
 
@inproceedings{wong2018newSMAT,
title={A New High Throughput and Area Efficient {SHA-3} Implementation},
author={Wong, Ming Ming and Jawad, Haj-Yahya and Suman, Sau and Chattopadhyay, Anupam},
booktitle={Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018)},
year={2018},
month=may,
pages={1--5},
location={Florence},
doi={10.1109/ISCAS.2018.8351649}
}
[34]K. Herath, A. Prakash, and T. Srikanthan, “Performance estimation of FPGA modules for modular design methodology using artificial neural network,” in Proceedings of the 14th International Symposium on Applied Reconfigurable Computing, Santorini, Greece, May 2018, pp. 105–118, DOI: 10.1007/978-3-319-78890-6_9.
 
@inproceedings{Herath2018PerformanceSMAT,
title={Performance Estimation of {FPGA} Modules for Modular Design Methodology using Artificial Neural Network},
author={Herath, Kalindu and Prakash, Alok and Srikanthan, Thambipillai},
booktitle={Proceedings of the 14th International Symposium on Applied Reconfigurable Computing},
year={2018},
month=may,
pages={105--118},
location={Santorini, Greece},
doi={10.1007/978-3-319-78890-6_9},
}
[35]S. Lam, J. Guiyuan, M. Wu, and B. Cao, “Area-time efficient streaming architecture for FAST and BRIEF detector,” IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1–1, Jun. 2018, DOI: 10.1109/TCSII.2018.2846683.
 
@article{Lam2018aAreaSMAT,
title={Area-Time Efficient Streaming Architecture for {FAST} and {BRIEF} Detector},
author={Lam, Siew-Kei and Guiyuan, Jiang and Wu, Meiqing and Cao, Bin},
journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
year={2018},
month=jun,
pages={1--1},
doi={10.1109/TCSII.2018.2846683},
}
[36]T. Perera, A. Prakash, C. N. Gamage, and T. Srikanthan, “Hybrid genetic algorithm for an on-demand first mile transit system using electric vehicles,” in Computational Science – ICCS 2018, Cham, Jun. 2018, pp. 98–113, DOI: 10.1007/978-3-319-93698-7_8.
 
@inproceedings{Perera2018HybridSMAT,
title={Hybrid Genetic Algorithm for an On-Demand First Mile Transit System Using Electric Vehicles},
author={Perera, Thilina and Prakash, Alok and Gamage, Chathura Nagoda and Srikanthan, Thambipillai},
booktitle={Computational Science -- ICCS 2018},
year={2018},
month=jun,
pages={98--113},
location={Cham},
doi={10.1007/978-3-319-93698-7_8},
}
[37]D. Wijesundera, A. Prakash, T. Srikanthan, and A. Ihalage, “Framework for rapid performance estimation of embedded soft core processors,” ACM Transactions on Reconfigurable Technology and Systems, vol. 11, pp. 9:1–9:21, Jul. 2018, DOI: 10.1145/3195801.
 
@article{Wijesundera2018FrameworkSMAT,
title={Framework for Rapid Performance Estimation of Embedded Soft Core Processors},
author={Wijesundera, Deshya and Prakash, Alok and Srikanthan, Thambipillai and Ihalage, Achintha},
journal={ACM Transactions on Reconfigurable Technology and Systems},
volume={11},
year={2018},
month=jul,
pages={9:1--9:21},
doi={10.1145/3195801},
}
[38]K. Herath, A. Prakash, U. C. H. Kanewala, and T. Srikanthan, “Communication-aware module placement for power reduction in large FPGA designs,” in 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 209–214, DOI: 10.1109/ISVLSI.2018.00047.
 
@inproceedings{Herath2018CommunicationSMAT,
title={Communication-Aware Module Placement for Power Reduction in Large {FPGA} Designs},
author={Herath, Kalindu and Prakash, Alok and Kanewala, Udaree Chathurangee Hiranthika and Srikanthan, Thambipillai},
booktitle={2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year={2018},
month=jul,
pages={209--214},
location={Hong Kong, China},
doi={10.1109/ISVLSI.2018.00047},
}
[39]R. Prasanna, S. Bhasin, J. Breier, and A. Chattopadhyay, “PPAP and iPPAP: PLL-based protection against physical attacks,” in 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 620–625, DOI: 10.1109/ISVLSI.2018.00118.
 
@inproceedings{Ravi2018PPAPSMAT,
title={{PPAP} and {iPPAP}: {PLL}-Based Protection Against Physical Attacks},
author={Prasanna, Ravi and Bhasin, Shivam and Breier, Jakub and Chattopadhyay, Anupam},
booktitle={2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year={2018},
month=jul,
pages={620--625},
location={Hong Kong, China},
doi={10.1109/ISVLSI.2018.00118},
}
[40]M. A. Elmohr, S. Kumar, M. Khairallah, and A. Chattopadhyay, “A hardware-efficient implementation of CLOC for on-chip authenticated encryption,” in 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 311–315, DOI: 10.1109/ISVLSI.2018.00064.
 
@inproceedings{Mahmoud2018ASMAT,
title={A Hardware-Efficient Implementation of {CLOC} for On-chip Authenticated Encryption},
author={Elmohr, Mahmoud A. and Kumar, Sachin and Khairallah, Mustafa and Chattopadhyay, Anupam},
booktitle={2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year={2018},
month=jul,
pages={311--315},
location={Hong Kong, China},
doi={10.1109/ISVLSI.2018.00064},
}
[41]D. Bhattacharjee and A. Chattopadhyay, “Synthesis, technology mapping and optimization for emerging technologies,” in 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 369–374, DOI: 10.1109/ISVLSI.2018.00074.
 
@inproceedings{Bhattacharjee2018SynthesisSMAT,
title={Synthesis, Technology Mapping and Optimization for Emerging Technologies},
author={Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
booktitle={2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year={2018},
month=jul,
pages={369--374},
location={Hong Kong, China},
doi={10.1109/ISVLSI.2018.00074},
}
[42]A. Baksi, V. Pudi, S. Mandal, and A. Chattopadhyay, “Lightweight ASIC implementation of AEGIS-128,” in 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 251–256, DOI: 10.1109/ISVLSI.2018.00054.
 
@inproceedings{baksi2018LightweightSMAT,
title={Lightweight {ASIC} Implementation of {AEGIS}-128},
author={Baksi, Anubhab and Pudi, Vikramkumar and Mandal, Swagata and Chattopadhyay, Anupam},
booktitle={2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
year={2018},
month=jul,
pages={251--256},
location={Hong Kong, China},
doi={10.1109/ISVLSI.2018.00054},
}
[43]B. Jasani, S. Lam, P. K. Meher, and M. Wu, “Threshold-guided design and optimization for harris corner detector architecture,” IEEE Transactions on Circuits and Systems for Video Technology, pp. 1–1, Sep. 2018, DOI: 10.1109/TCSVT.2017.2757998.
 
@article{Jasani2018ThresholdSMAT,
title={Threshold-Guided Design and Optimization for Harris Corner Detector Architecture},
author={Jasani, Bhavan and Lam, Siew-Kei and Meher, Pramod Kumar and Wu, Meiqing},
journal={IEEE Transactions on Circuits and Systems for Video Technology},
year={2018},
month=sep,
pages={1--1},
doi={10.1109/TCSVT.2017.2757998},
}
[44]S. Lam, T. C. Lim, M. Wu, B. Cao, and B. Jasani, “Area-time efficient FAST corner detector using data-path transposition,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, pp. 1224–1228, Sep. 2018, DOI: 10.1109/TCSII.2017.2752259.
 
@article{Lam2018bAreaSMAT,
title={Area-Time Efficient {FAST} Corner Detector Using Data-Path Transposition},
author={Lam, Siew-Kei and Lim, Teck Chuan and Wu, Meiqing and Cao, Bin and Jasani, Bhavan},
journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
volume={65},
year={2018},
month=sep,
pages={1224--1228},
doi={10.1109/TCSII.2017.2752259},
}
[45]A. Prakash, C. T. Clarke, S. K. Lam, and T. Srikanthan, “Rapid memory-aware selection of hardware accelerators in programmable SoC design,” IEEE Transactions on Very Large Scale Integration Systems, vol. 26, pp. 445–456, Sep. 2018, DOI: 10.1109/TVLSI.2017.2769125.
 
@article{prakash2018rapidSMAT,
title={Rapid Memory-Aware Selection of Hardware Accelerators in Programmable {SoC} Design},
author={Prakash, Alok and Clarke, Christopher T. and Lam, Siew Kei and Srikanthan, Thambipillai},
journal={IEEE Transactions on Very Large Scale Integration Systems},
volume={26},
year={2018},
month=sep,
pages={445--456},
doi={10.1109/TVLSI.2017.2769125}
}
[46]S. Kumar, S. Jha, S. K. Pandey, and A. Chattopadhyay, “A security model for intelligent vehicles and smart traffic infrastructure,” in Proceedings of the IEEE Intelligent Vehicles Symposium , 2018, accepted.
 
@inproceedings{Sachin2018ASMAT,
title={A Security Model for Intelligent Vehicles and Smart Traffic Infrastructure},
author={Kumar, Sachin and Jha, Sonu and Pandey, Sumit Kumar and Chattopadhyay, Anupam},
booktitle={Proceedings of the IEEE Intelligent Vehicles Symposium },
year={2018},
}
[47]M. Swagata, B. Debjyoti, T. Yaswanth, and A. Chattopadhyay, “ReRAM-based in-memory computation of galois field arithmetic,” in Proceedings of the IEEE/IFIP VLSI-SoC, 2018, accepted.
 
@inproceedings{Swagata2018ReRAMSMAT,
title={{ReRAM}-based In-Memory Computation of Galois Field Arithmetic},
author={Swagata, Mandal and Debjyoti, Bhattacharjee and Yaswanth, Tavva and Chattopadhyay, Anupam},
booktitle={Proceedings of the IEEE/IFIP VLSI-SoC},
year={2018},
}
[48]T. Perera, C. N. Gamage, A. Prakash, and T. Srikanthan, “A simulation framework for a real-time demand responsive public transit system,” in Proceedings of the IEEE 21st International Conference on Intelligent Transportation Systems, 2018, accepted.
 
@inproceedings{Perera2018aASMAT,
title={A Simulation Framework for a Real-Time Demand Responsive Public Transit System},
author={Perera, Thilina and Gamage, Chathura Nagoda and Prakash, Alok and Srikanthan, Thambipillai},
booktitle={Proceedings of the IEEE 21st International Conference on Intelligent Transportation Systems},
year={2018},
}
[49]T. Perera, A. Prakash, and T. Srikanthan, “A hybrid methodology for optimal fleet management in an electric vehicle based flexible bus service,” in Proceedings of the 14th International Conference on Control, Automation, Robotics and Vision, 2018, accepted.
 
@inproceedings{Perera2018bASMAT,
title={A Hybrid Methodology for Optimal Fleet Management in an Electric Vehicle Based Flexible Bus Service},
author={Perera, Thilina and Prakash, Alok and Srikanthan, Thambipillai},
booktitle={Proceedings of the 14th International Conference on Control, Automation, Robotics and Vision},
year={2018},
}
[50]D. Wijesundera, A. Prakash, T. Perera, K. Herath, and T. Srikanthan, “Wibheda: framework for data dependency-aware multi-constrained hardware-software partitioning in FPGA-based SoCs for IoT devices,” in Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2018, in press.
 
@inproceedings{Wijesundera2018aFrameworkSMAT,
title={Wibheda: Framework for Data Dependency-aware Multi-constrained Hardware-Software Partitioning in {FPGA}-based {SoCs} for {IoT} Devices},
author={Wijesundera, Deshya and Prakash, Alok and Perera, Thilina and Herath, Kalindu and Srikanthan, Thambipillai},
booktitle={Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines},
year={2018},
}
[51]D. Wijesundera, A. Prakash, T. Perera, K. Herath, and T. Srikanthan, “Wibheda+: framework for data dependency-aware multi-constrained hardware-software partitioning in FPGA-based socs for IoT applications,” in Proceedings of the 9th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2018, in press.
 
@inproceedings{Wijesundera2018bFrameworkSMAT,
title={Wibheda+: Framework for Data Dependency-aware Multi-constrained Hardware-Software Partitioning in {FPGA}-based SoCs for {IoT} Applications},
author={Wijesundera, Deshya and Prakash, Alok and Perera, Thilina and Herath, Kalindu and Srikanthan, Thambipillai},
booktitle={Proceedings of the 9th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies},
year={2018},
}
[52]A. Khalid, G. Paul, and A. Chattopadhyay, “Domain-specific high level synthesis,” in Springer In Press, 2018, in press.
 
@inproceedings{Ayesha2018DomainSMAT,
title={Domain-specific High Level Synthesis},
author={Khalid, Ayesha and Paul, Goutam and Chattopadhyay, Anupam},
booktitle={Springer In Press},
year={2018},
}

Other output

[53]S. Kumar, J. Haj-Yahya, M. Khairallah, M. Elmohr, and A. Chattopadhyay, “A comprehensive performance analysis of hardware implementations of CAESAR candidates,” in Cryptology ePrint Archive, Report 2017/1261, 2017, 2017, pp. 1–16, [Online]. Available: https://eprint.iacr.org/2017/1261.pdf.
 
@inproceedings{Kumar2017ASMAT,
title={A Comprehensive Performance Analysis of Hardware Implementations of {CAESAR} Candidates},
author={Kumar, Sachin and Haj-Yahya, Jawad and Khairallah, Mustafa and Elmohr, Mahmoud and Chattopadhyay, Anupam},
booktitle={Cryptology ePrint Archive, Report 2017/1261, 2017},
year={2017},
pages={1--16},
url={https://eprint.iacr.org/2017/1261.pdf},
}

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