Communication-aware Module Placement for Power Reduction in Large FPGA Designs,

K. Herath, A. Prakash, U. C. H. Kanewala, and T. Srikanthan, “Communication-aware Module Placement for Power Reduction in Large FPGA Designs,” in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 209–214, DOI: 10.1109/ISVLSI.2018.00047.

Scroll to Top