Past Research Group

Sensing and Management for Agile Transport

SMAT focusses on developing intelligent sensing technologies to support and enforce traffic management of the SRT layer.

Project Details

Status

Completed

Type

Research group

Overview

SMAT focusses on developing intelligent sensing technologies to support and enforce traffic management of the SRT layer. This involves the development of robust and secure vision based sensing methods for collaborative computing and crowd sourcing. The underlying research in SMAT will lead to a better understanding of the advantage and limitations of utilizing real-time data to assist travellers in an Agile Transportation System.

Research

Architecture-Aware Algorithms for Low-Cost Sensing

In order to provide for scalable vision based crowd sourcing for a dense urban public transport system, such as in Singapore, low-complexity sensing techniques are critical to justify mass volume adoption. Architecture-efficient algorithms are being developed to implement low-complexity and real-time vision-based traffic sensors. The robustness of such algorithms will be evaluated to ensure they withstand the varying weather conditions and complex conditions on a road segment.

Techniques for Vehicle Breakdown and Accident Detection

Vision based techniques are being devised to accurately establish traffic incidents and traffic violations. Computationally inexpensive computer vision algorithms are being developed to perform localized monitoring of current traffic condition. Vision based sensors will be used to detect traffic law violations (e.g. entering priority lanes, illegal parking in priority lanes, illegal turns, etc.). It is envisaged that mass-deployable real-time law enforcement solutions would ultimately ensure smooth traffic flow for SRTs.

Real-Time Scene Understanding for Congestion Management

Persistent congestions can be automatically identified through real-time scene understanding techniques. Crowd sourcing methods are being adopted by installing scene understanding sensors in vehicles to detect congestion. The relevant authorities can then take necessary actions to alleviate such unanticipated persistent congestion patterns that emerge over time.

Passive Sensing Techniques using Smartphone Location Data

The problem of inferring the mobility details of users from sequences of smartphone location samples involves considerable uncertainty, especially if the data is noisy and temporally sparse. Therefore, we intend to adopt a suitable probabilistic framework for solving this problem. To be able to process real-time data from a large number of users, the algorithms should have low latency and high computational efficiency. Therefore, are exploring optimization techniques to reduce the runtime and latency of the proposed methods. The developed solutions will be subjected to extensive evaluations using both real data as well as synthetic data obtained from traffic simulation environments. Robust statistical methods will be explored for aggregating information extracted from individual mobility traces in order to estimate the overall travel demand.

Secure Autonomous Traffic Security

A security-enabled sensory network protocol that satisfies real-time constraints is being developed using a virtual traffic simulation environment. The proposed network protocol will be deployed and benchmarked with off-the-shelf micro-controllers and FPGA development boards. Side-channel attack/tamper-resistant low-cost cryptographic accelerators for Internet of Things (IoT) communication will be developed such that the encryption/decryption modules are physically resistant to reasonably sophisticated side-channel attacks.

Publications

  1. [67] D. Piyasena, R. Wickramasinghe, D. Paul, S. K. Lam, and M. Wu, “Lowering dynamic power of a stream-based cnn hardware accelerator,” in 2019 IEEE 21st International Workshop on Multimedia Signal Processing (MMSP), Kuala Lumpur, Malaysia, Sep. 2019, pp. 1–6, DOI: 10.1109/MMSP.2019.8901777
  2. [66] D. Piyasena, R. Wickramasinghe, D. Paul, S. K. Lam, and M. Wu, “Reducing dynamic power in streaming cnn hardware accelerators by exploiting computational redundancies,” in 2019 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, Spain, Sep. 2019, pp. 354–359, DOI: 10.1109/FPL.2019.00063
  3. [65] T. H. Pham, P. Tran, and S. K. Lam, “High-Throughput and area-optimized architecture for rbrief feature extraction,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, pp. 747–756, Dec. 2018, DOI: 10.1109/TVLSI.2018.2881105
  4. [64] A. Baksi, D. Saha, and S. Sarkar, “To infect or not to infect: a critical analysis of infective countermeasures in fault attacks,” Journal of Cryptographic Engineering (JCEN), Springer, 2020, accepted
  5. [63] P. He, G. Jiang, S. K. Lam, and Y. Sun, “Learning heterogeneous traffic patterns for travel time prediction of bus journeys,” Information Sciences, vol. 512, Elsevier, pp. 1394–1406, Feb. 2020, DOI: 10.1016/j.ins.2019.10.073
  6. [62] T. Perera, A. Prakash, D. Wijesundera, T. Srikanthan, and C. N. Gamage, “Cluster-first, route-second heuristic for EV scheduling in on-demand public transit,” in Proceedings of the 9th International Conference on Cybernetics and Intelligent Systems and Robotics, Automation and Mechatronics (CIS-RAM), 2019, accepted
  7. [61] T. Perera, A. Prakash, and T. Srikanthan, “Genetic algorithm based dynamic scheduling of EV in a demand responsive bus service for first mile transit,” in Proceedings of the 22nd International Conference on Intelligent Transportation Systems (ITSC), Auckland, New Zealand, New Zealand: IEEE, Oct. 2019, pp. 3322–3327, DOI: 10.1109/ITSC.2019.8917141
  8. [60] P. He, Y. Sun, G. Jiang, and S. K. Lam, “Predicting travel time of bus journeys with alternative bus services,” in Proceedings of the 2019 IEEE International Conference on Data Mining Workshops, ICDM Workshops 2019, Beijing, China: IEEE, Nov. 2019, pp. 114–123, DOI: 10.1109/ICDMW.2019.00027
  9. [59] G. Jiang, S. K. Lam, F. Ning, P. He, and J. Xie, “Peak-hour vehicle routing for first-mile transportation: problem formulation and algorithms,” IEEE Transactions on Intelligent Transportation Systems, IEEE, pp. 1–14, 2019, DOI: 10.1109/TITS.2019.2926065
  10. [58] G. R. Jagadeesh and T. Srikanthan, “Fast computation of clustered many-to-many shortest paths and its application to map matching,” ACM Transactions on Spatial Algorithms and Systems, vol. 5, no. 3, ACM, pp. 17:1–17:20, Aug. 2019, DOI: 10.1145/3329676
  11. [57] T. Perera, A. Prakash, and T. Srikanthan, “Genetic algorithm based EV scheduling for on-demand public transit system,” in Proceedings of the 2019 International Conference on Computational Science – ICCS 2019, Faro, Portugal, Jun. 2019, pp. 595–603, DOI: 10.1007/978-3-030-22750-0_56
  12. [56] K. Garg, N. Ramakrishnan, A. Prakash, and T. Srikanthan, “Rapid and robust background modeling technique for low-cost road traffic surveillance systems,” IEEE Transactions on Intelligent Transportation Systems, IEEE, pp. 1–12, May 2019, DOI: 10.1109/TITS.2019.2917560
  13. [55] Y. Sun, G. Jiang, S. K. Lam, S. Chen, and P. He, “Bus travel speed prediction using attention network of heterogeneous correlation features,” in Proceedings of the 2019 SIAM International Conference on Data Mining (SDM), Calgary, Alberta, Canada, May 2019, pp. 73–81, DOI: 10.1137/1.9781611975673.9
  14. [54] K. Garg, N. Ramakrishnan, A. Prakash, S. Thambipillai, and P. Bhatt, “Rapid technique to eliminate moving shadows for accurate vehicle detection,” in Proceedings of the 2019 IEEE Winter Conference on Applications of Computer Vision (WACV), Hawaii, USA: IEEE, Jan. 2019, pp. 1970–1978, DOI: 10.1109/WACV.2019.00214
  15. [53] A. Khalid, G. Paul, and A. Chattopadhyay, “Domain specific high-level synthesis for cryptographic workloads,” in Computer Architecture and Design Methodologies, Springer Singapore, 2019, DOI: 10.1007/978-981-10-1070-5
  16. [52] D. Wijesundera, A. Prakash, T. Perera, K. Herath, and T. Srikanthan, “Wibheda+: framework for data dependency-aware multi-constrained hardware-software partitioning in FPGA-based SoCs for IoT applications,” in Proceedings of the 9th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Toronto, ON, Canada: ACM, Jun. 2018, pp. 3:1–3:6, DOI: 10.1145/3241793.3241796
  17. [51] D. Wijesundera, A. Prakash, T. Perera, K. Herath, and T. Srikanthan, “Wibheda: framework for data dependency-aware multi-constrained hardware-software partitioning in FPGA-based SoCs for IoT devices,” in Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, Boulder, CO, USA: IEEE, Apr. 2018, pp. 213-213, DOI: 10.1109/FCCM.2018.00047
  18. [50] M. Swagata, B. Debjyoti, T. Yaswanth, and A. Chattopadhyay, “ReRAM-based in-memory computation of galois field arithmetic,” in Proceedings of the IEEE/IFIP VLSI-SoC, Verona, Italy, Italy: IEEE, Oct. 2018, pp. 1-6, DOI: 10.1109/VLSI-SoC.2018.8644772
  19. [49] S. Kumar, S. Jha, S. K. Pandey, and A. Chattopadhyay, “A security model for intelligent vehicles and smart traffic infrastructure,” in Proceedings of the IEEE Intelligent Vehicles Symposium, Changshu, China: IEEE, Jun. 2018, pp. 162-167, DOI: 10.1109/IVS.2018.8500423
  20. [48] P. He, G. Jiang, S. K. Lam, and D. Tang, “Travel-time prediction of bus journey with multiple bus trips,” IEEE Transactions on Intelligent Transportation Systems, IEEE, 2018, DOI: 10.1109/TITS.2018.2883342
  21. [47] P. Tran, T. H. Pham, S. K. Lam, M. Wu, and B. A. Jasani, “Stream-Based ORB feature extractor with dynamic power optimization,” in Proceedings of the 2018 International Conference on Field-Programmable Technology (FPT), IEEE, Dec. 2018, pp. 94–101, DOI: 10.1109/FPT.2018.00024
  22. [46] T. Perera, A. Prakash, and T. Srikanthan, “A hybrid methodology for optimal fleet management in an electric vehicle based flexible bus service,” in Proceedings of the 15th International Conference on Control, Automation, Robotics and Vision (ICARCV), Singapore, Nov. 2018, pp. 331–336, DOI: 10.1109/ICARCV.2018.8581345
  23. [45] T. Perera, C. N. Gamage, A. Prakash, and T. Srikanthan, “A simulation framework for a real-time demand responsive public transit system,” in Proceedings of the 21st International Conference on Intelligent Transportation Systems (ITSC), Maui, Hawaii, Nov. 2018, pp. 608–613, DOI: 10.1109/ITSC.2018.8569281
  24. [44] B. Jasani, S. K. Lam, P. K. Meher, and M. Wu, “Threshold-guided design and optimization for harris corner detector architecture,” IEEE Transactions on Circuits and Systems for Video Technology, pp. 1–1, Sep. 2018, DOI: 10.1109/TCSVT.2017.2757998
  25. [43] S. K. Lam, T. C. Lim, M. Wu, B. Cao, and B. Jasani, “Area-time efficient FAST corner detector using data-path transposition,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, pp. 1224–1228, Sep. 2018, DOI: 10.1109/TCSII.2017.2752259
  26. [42] A. Prakash, C. T. Clarke, S. K. Lam, and T. Srikanthan, “Rapid memory-aware selection of hardware accelerators in programmable SoC design,” IEEE Transactions on Very Large Scale Integration Systems, vol. 26, pp. 445–456, Sep. 2018, DOI: 10.1109/TVLSI.2017.2769125
  27. [41] D. Wijesundera, A. Prakash, T. Srikanthan, and A. Ihalage, “Framework for rapid performance estimation of embedded soft core processors,” ACM Transactions on Reconfigurable Technology and Systems, vol. 11, pp. 9:1–9:21, Jul. 2018, DOI: 10.1145/3195801
  28. [40] A. Baksi, V. Pudi, S. Mandal, and A. Chattopadhyay, “Lightweight ASIC implementation of AEGIS-128,” in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 251–256, DOI: 10.1109/ISVLSI.2018.00054
  29. [39] D. Bhattacharjee and A. Chattopadhyay, “Synthesis, technology mapping and optimization for emerging technologies,” in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 369–374, DOI: 10.1109/ISVLSI.2018.00074
  30. [38] M. A. Elmohr, S. Kumar, M. Khairallah, and A. Chattopadhyay, “A hardware-efficient implementation of CLOC for on-chip authenticated encryption,” in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 311–315, DOI: 10.1109/ISVLSI.2018.00064
  31. [37] R. Prasanna, S. Bhasin, J. Breier, and A. Chattopadhyay, “PPAP and iPPAP: PLL-based protection against physical attacks,” in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 620–625, DOI: 10.1109/ISVLSI.2018.00118
  32. [36] K. Herath, A. Prakash, U. C. H. Kanewala, and T. Srikanthan, “Communication-aware module placement for power reduction in large FPGA designs,” in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Jul. 2018, pp. 209–214, DOI: 10.1109/ISVLSI.2018.00047
  33. [35] T. Perera, A. Prakash, C. N. Gamage, and T. Srikanthan, “Hybrid genetic algorithm for an on-demand first mile transit system using electric vehicles,” in Proceedings of the 2018 International Conference on Computational Science – ICCS 2018, Wuxi, China, Jun. 2018, pp. 98–113, DOI: 10.1007/978-3-319-93698-7_8
  34. [34] K. Herath, A. Prakash, and T. Srikanthan, “Performance estimation of FPGA modules for modular design methodology using artificial neural network,” in Proceedings of the 14th International Symposium on Applied Reconfigurable Computing, Santorini, Greece, May 2018, pp. 105–118, DOI: 10.1007/978-3-319-78890-6_9
  35. [33] M. M. Wong, J. Haj-Yahya, S. Suman, and A. Chattopadhyay, “A new high throughput and area efficient SHA-3 implementation,” in Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018), Florence, May 2018, pp. 1–5, DOI: 10.1109/ISCAS.2018.8351649
  36. [32] V. Pudi, A. Chattopadhyay, and K. Y. Lam, “Efficient and lightweight quantized compressive sensing using mu-law,” in Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018), Florence, May 2018, pp. 1–5, DOI: 10.1109/ISCAS.2018.8351505
  37. [31] S. Kumar, J. Haj-Yahya, and A. Chattopadhyay, “Efficient hardware accelerator for NORX authenticated encryption,” in Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS-2018), Florence, May 2018, pp. 195–198, DOI: 10.1109/ISCAS.2018.8351145
  38. [30] T. Vatwani, A. Dutt, D. Bhattacharjee, and A. Chattopadhyay, “Floating point multiplication mapping on ReRAM based in-memory computing architecture,” in Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems (VLSID), Pune, India, Apr. 2018, pp. 439–444, DOI: 10.1109/VLSID.2018.104
  39. [29] D. Bhattacharjee, L. Amaru, and A. Chattopadhyay, “Technology-aware logic synthesis for ReRAM based in-memory computing,” in Proceedings of the 2018 Design, Automation Test in Europe Conference Exhibition (DATE), Dresden, Germany, Mar. 2018, pp. 1435–1440, DOI: 10.23919/DATE.2018.8342237
  40. [28] M. Khairallah, R. Sadhukhan, R. Samanta, J. Breier, S. Bhasin, R. S. Chakraborty, A. Chattopadhyay, and D. Mukhopadhyay, “DFARPA: differential fault attack resistant physical design automation,” in Proceedings of the 2018 Design, Automation Test in Europe Conference and Exhibition (DATE), Dresden, Germany, Mar. 2018, pp. 1171–1174, DOI: 10.23919/DATE.2018.8342190
  41. [27] V. Pudi, A. Chattopadhyay, and K. Y. Lam, “Secure and lightweight compressive sensing using stream cipher,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, pp. 371–375, Mar. 2018, ISSN: 1549-7747, DOI: 10.1109/TCSII.2017.2715659
  42. [26] S. K. Lam, G. Jiang, M. Wu, and B. Cao, “Area-time efficient streaming architecture for FAST and BRIEF detector,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, IEEE, pp. 282–286, Feb. 2018, DOI: 10.1109/TCSII.2018.2846683
  43. [25] A. Burg, A. Chattopadhyay, and K. Y. Lam, “Wireless communication and security issues for cyber-physical systems and the internet-of-things,” Proceedings of the IEEE, vol. 106, pp. 38–60, Jan. 2018, DOI: 10.1109/JPROC.2017.2780172
  44. [24] M. Wu, S. K. Lam, and T. Srikanthan, “A framework for fast and robust visual odometry,” IEEE Transactions on Intelligent Transportation Systems, vol. 18, no. 12, pp. 3433–3448, Dec. 2017, DOI: 10.1109/TITS.2017.2685433
  45. [23] S. K. Lam, R. K. Bijarniya, and M. Wu, “Lowering dynamic power in stream-based harris corner detection architecture,” in Proceedings of the 2017 International Conference on Field Programmable Technology (ICFPT), Melbourne, VIC, Australia, Dec. 2017, pp. 176–182, DOI: 10.1109/FPT.2017.8280136
  46. [22] G. R. Jagadeesh and T. Srikanthan, “Online map-matching of noisy and sparse location data with hidden markov and route choice models,” IEEE Transactions on Intelligent Transportation Systems, vol. 18, no. 9, pp. 2423–2434, Dec. 2017, DOI: 10.1109/TITS.2017.2647967
  47. [21] A. Chattopadhyay and K. Y. Lam, “Security of autonomous vehicle as a cyber-physical system,” in Proceedings of the 7th IEEE International Symposium on Embedded Computing and System Design (ISED-2017), India, Dec. 2017, pp. 1–6, DOI: 10.1109/ISED.2017.8303906
  48. [20] S.-K. Lam, T. C. Lim, M. Wu, B. Cao, and B. Jasani, “Data-path unrolling with logic folding for area-time-efficient FPGA-based FAST corner detector,” Journal of Real-Time Image Processing, Oct. 2017, DOI: 10.1007/s11554-017-0725-0
  49. [19] C. Zhou, M. Wu, and S. K. Lam, “Fast and accurate pedestrian detection using dual-stage group cost-sensitive realboost with vector form filters,” in Proceedings of the 25th ACM Multimedia, Mount View, USA, Oct. 2017, pp. 735–743, DOI: 10.1145/3123266.3123303
  50. [18] K. Garg, A. Prakash, and T. Srikanthan, “Low complexity techniques for robust real-time traffic incident detection,” in Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems (ITSC), Yokohama, Japan, Oct. 2017, pp. 1–8, DOI: 10.1109/ITSC.2017.8317740
  51. [17] T. Perera, A. Prakash, and T. Srikanthan, “A scalable heuristic algorithm for demand responsive transportation for first mile transit,” in Proceedings of the 21st IEEE International Conference on Intelligent Engineering Systems, Larnaca, Cyprus, Oct. 2017, pp. 157–162, DOI: 10.1109/INES.2017.8118547
  52. [16] S. D. Kumar, S. Patranabis, J. Breier, D. Mukhopadhyay, S. Bhasin, A. Chattopadhyay, and A. Baksi, “A practical fault attack on ARX-like ciphers with a case study on ChaCha20,” in Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Taipei, Taiwan, Sep. 2017, pp. 33–40, DOI: 10.1109/FDTC.2017.14
  53. [15] C. Zhou, M. Wu, and S. K. Lam, “Group cost-sensitive boosting with multi-scale decorrelated filters for pedestrian detection,” in Proceedings of the Twenty Eighth British Machine Vision Conference, London, UK: BMVA Press, Sep. 2017, pp. 48.1–48.12, DOI: 10.5244/C.31.48
  54. [14] S. P. Kadiyala, V. K. Pudi, and S. K. Lam, “Approximate compressed sensing for hardware-efficient image compression,” in Proceedings of the 30th IEEE International System-on-Chip Conference (SOCC), Munich, Germany, Sep. 2017, pp. 340–345, DOI: 10.1109/SOCC.2017.8226074
  55. [13] G. Jiang, S. K. Lam, S. Yidan, L. Tu, and J. Wu, “Joint charging tour planning and depot positioning for wireless sensor networks using mobile chargers,” IEEE/ACM Transactions on Networking, vol. 25, pp. 2250–2266, Aug. 2017, ISSN: 1063-6692, DOI: 10.1109/TNET.2017.2684159
  56. [12] D. Wijesundera, A. Ihalage, A. Prakash, and T. Srikanthan, “High speed performance estimation of embedded hard-core processors in FPGA-based socs,” in Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Bochum, Germany, Jun. 2017, pp. 2:1–2:6, ISBN: 978-1-4503-5316-8, DOI: 10.1145/3120895.3120902
  57. [11] K. Herath, A. Prakash, J. Guiyuan, and T. Srikanthan, “Communication-aware partitioning for energy optimization of large FPGA designs,” in Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, Alberta, Canada, May 2017, pp. 407–410, DOI: 10.1145/3060403.3060441
  58. [10] A. Chattopadhyay, A. Prakash, and M. Shafique, “Secure cyber-physical systems: current trends, tools and open research problems,” in Proceedings of the 2017 Design, Automation Test in Europe Conference (DATE), Lausanne, Switzerland, Mar. 2017, pp. 1104–1109, DOI: 10.23919/DATE.2017.7927154
  59. [9] D. Bhattacharjee, V. Pudi, and A. Chattopadhyay, “SHA-3 implementation using reram based in-memory computing architecture,” in Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, Mar. 2017, pp. 325–330, DOI: 10.1109/ISQED.2017.7918336
  60. [8] A. Easwaran, A. Chattopadhyay, and S. Bhasin, “A systematic security analysis of real-time cyber-physical systems,” in Proceedings of the 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, Jan. 2017, pp. 206–213, DOI: 10.1109/ASPDAC.2017.7858321
  61. [7] V. Pudi, A. Chattopadhyay, and T. Srikanthan, “Modified projected landweber method for compressive-sensing reconstruction of images with non-orthogonal matrices,” in Proceedings of the 2016 International Symposium on Integrated Circuits (ISIC), Singapore, Dec. 2016, pp. 1–4, DOI: 10.1109/ISICIR.2016.7829716
  62. [6] D. Wijesundera, A. Prakash, and T. Srikanthan, “Rapid design space exploration for soft core processor customization and selection,” in Proceedings of the 2016 International Conference on Field-Programmable Technology (FPT), Xi’an, China, Dec. 2016, pp. 185–188, DOI: 10.1109/FPT.2016.7929529
  63. [5] G. R. Jagadeesh and T. Srikanthan, “Heuristic optimizations for high-speed low-latency online map matching with probabilistic sequence models,” in Proceedings of the 19th International Conference on Intelligent Transportation Systems (ITSC 2016), Rio de Janeiro, Brazil, Nov. 2016, pp. 2565–2570, DOI: 10.1109/ITSC.2016.7795968
  64. [4] M. Wu, C. Zhou, and T. Srikanthan, “Robust and low complexity obstacle detection and tracking,” in 2016 IEEE 19th International Conference on Intelligent Transportation Systems (ITSC), Brazil, Nov. 2016, pp. 1249–1254, DOI: 10.1109/ITSC.2016.7795717
  65. [3] A. Chattopadhyay, V. Pudi, A. Baksi, and T. Srikanthan, “FPGA based cyber security protocol for automated traffic monitoring systems: proposal and implementation,” in Proceedings of the 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, USA, Jul. 2016, pp. 18–23, DOI: 10.1109/ISVLSI.2016.97
  66. [2] D. Wijesundera, A. Prakash, S. K. Lam, and T. Srikanthan, “Exploiting configuration dependencies for rapid area-efficient customization of soft-core processors,” in Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, Sankt Goar, Germany, May 2016, pp. 163–172, ISBN: 978-1-4503-4320-6, DOI: 10.1145/2906363.2906385
  67. [1] K. Garg, S. K. Lam, T. Srikanthan, and A. Vedika, “Real-time road traffic density estimation using block variance,” in Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision (WACV), Lake Placid, NY, USA, Mar. 2016, pp. 1–9, DOI: 10.1109/WACV.2016.7477607
  68. [2] M. Alam, S. Bhattacharya, D. Mukhopadhyay, and A. Chattopadhyay, “RAPPER: ransomware prevention via performance counters,” Cryptography and Security, vol. 25, pp. 1–7, Feb. 2018
  69. [1] S. Kumar, J. Haj-Yahya, M. Khairallah, M. Elmohr, and A. Chattopadhyay, “A comprehensive performance analysis of hardware implementations of CAESAR candidates,” in Cryptology ePrint Archive, Report 2017/1261, 2017, 2017, pp. 1–16
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